Embodiments of the present invention relate to integrated circuits (ICs), and, more particularly, to cleaning processes to control contamination from metal comprising gate dielectrics and fabrication methods for ICs.
Conventional methods of creating CMOS devices use gate electrodes comprising polysilicon that is deposited and patterned over a layer of gate oxide. With the continued decrease in device dimensions, the gate length for sub-micron devices has been decreased to 0.25 μm or less. As gate dielectrics are reduced to this thickness and beyond, a practical and theoretical limit is being approached to the thermal oxidation of a silicon surface for the formation of a layer of gate oxide. In order to meet this challenge, the semiconductor industry is developing materials that can be used as replacement of the thermal oxides that are typically used for the gate dielectric layer.
For example, for gate electrodes that are created with a layer of gate dielectric having an equivalent oxide thickness (EOT) of 14 Angstroms, the leakage current of the gate dielectric, typically comprising a silicon oxide or oxynitride layer, is in generally in excess of 10 A/cm2. This results in high power consumption of the gate electrode and concerns of gate dielectric reliability, thus having a serious negative impact on the electrical performance of the gate electrode. For this reason, high-k metal oxide materials have begun replacing the thermal oxide gate dielectrics. Since the dielectric constant of most metal oxide materials is higher than the dielectric constant of thermally grown oxide, a thicker layer of metal oxide can be deposited while still achieving the required a value of EOT that is comparable to the EOT value of a thinner layer of thermal gate oxide material. The thicker layer of metal oxide for the gate dielectric reduces the gate-to-channel leakage current without having a negative impact on CMOS device performance and is therefore generally advantageous.
However, the high-k metal oxide material is deposited relatively early in the process, being deposited before gate electrode (gate electrode, barrier metal and gate electrode filler) processing. This early portion of the process flow has historically been without any metal comprising layers. Having all non-metal layers generally allows the same processing tools to be used for a wide variety of processing steps, generally without processing restrictions. However, the introduction of high-k materials for use as the gate dielectric has complicated this situation since many of these materials comprise a metal, thus requiring separate processing tools for processing wafers having metal comprising gate dielectrics layers and wafers having all non-metal comprising layers to avoid or at least limit metal cross-contamination. Dedicated processing tools for wafers having non-metal comprising layers and wafers having metal comprising layers increases final die cost by requiring more processing tools, and an increase in required floor space for the added tools.